Wireless technology using ultra-wide frequency bands (UWB: Ultra Wideband) uses a frequency synthesizer which may rapidly switch oscillation frequencies. For example, in multiband OFDM, which is a promising candidate as a UWB transmission method, so-called “frequency hopping” is employed in which a frequency band is divided into a plurality of bands, and the frequency band used is switched rapidly. For example, suppose that three frequency bands, with different central frequencies of for example 3432 MHz, 3960 MHz, and 4488 MHz, are utilized by switching appropriately using frequency hopping. In this case, it is preferable to switch frequency bands with high switching speed less than for example 9.5 ns.
FIG. 1 depicts frequency hopping of a frequency synthesizer. The horizontal axis indicates time, and the vertical axis is the output frequency of the frequency synthesizer. As depicted in the figure, the frequency synthesizer switch the output frequency from f2 to f1, preferably in a short time Dt (less than 9.5 ns).
On the other hand, a frequency synthesizer is realized by a PLL circuit which generates a high-speed clock phase-synchronized to a reference clock which is generated by a local oscillator or similar. That is, by switching the frequency division ratio of the frequency divider of the PLL circuit, an output clock at different frequencies may be generated.
FIG. 2 depicts the output frequency characteristic of a PLL circuit. In the case of a PLL circuit, the time Tlock until lock-in, at which the oscillation frequency is stabilized in the feedback loop, is of microsecond order, and lock-in within the short time Dt depicted in FIG. 1 is not easy.
There have been various proposals for shortening the lock-in time Tlock in a PLL circuit, as for example in Japanese Laid-open Patent Publication No. 07-288471, Japanese Laid-open Patent Publication No. 2002-57578, Japanese Laid-open Patent Publication No. 11-316618, and Japanese Laid-open Patent Publication No. 2001-339301. For example, in Japanese Laid-open Patent Publication No. 07-288471, when the PLL circuit frequency division ratio is switched, the time constant of a filter in the PLL loop is reduced and the responsiveness heightened, and the time constant is increased gradually each time undershoot or overshoot occur to reduce the responsiveness, in order to shorten the time to lock-in.
In Japanese Laid-open Patent Publication No. 2001-339301, a method is proposed in which a voltage-controlled oscillator (VCO) within the PLL circuit has a plurality of control codes to set the resonance frequency, and prior to normal operation, the optimum control code is searched for and selected from a plurality of control codes setting the resonance frequency of the VCO, the control code is set such that the VCO output frequency is within the desired frequency range, and thereafter lock-in operation is performed by the PLL loop circuit through normal operation. By this means, the effective dynamic range of the VCO may be broadened.
As a separate proposal, in order to enable frequency hopping between the above three frequency bands, three different PLL circuits each with different frequency division ratios may be provided, and output clocks, phase-synchronized with a reference clock, may be output in the respective frequency bands by the PLL circuits, with switching of the PLL circuit output clocks performed. By means of this configuration, frequency hopping in a short time is possible.
However, when employing a configuration in which a plurality of PLL circuits are provided and switching between the output clocks thereof is performed, the circuit scale is increased and power consumption also increases, so that such a solution is not practical. A method is preferable such that the output clock frequency may be rapidly switched in a single PLL circuit.